1. Field of the Invention
This invention relates to a control device for an image memory, and more particularly to an image memory control device wherein writing of video data into an image memory and read/write access of a computer to the image memory are performed in a same system.
2. Description of the Related Art
In recent years, image data processing systems wherein a video image is fetched into a computer to process the image data have been put into practical use.
In a system of the type mentioned, an analog video image is digitized and written into an image memory, and the data are fetched into and processed by a computer while the data are displayed on a monitor display unit of the computer so that the image information may be recognized by an operator. Accordingly, high speed memory access is required, and particularly it is required for the computer to read the memory at a high rate to fetch a necessary and sufficient amount of data into the computer in a unit time.
One of systems of the type described above is disclosed, for example, in Japanese Patent Laid-Open Application No. Heisei 4-88534 wherein, taking notice of the data structure wherein image data are inclined to gather in a particular area and are frequently stored cyclically into addresses of an image memory spaced by a fixed difference from each other, read access to the image memory is performed in the following manner to achieve high speed operation. In particular, read addresses demanded from a computer are successively supervised to detect a difference between the addresses, and a read address for a next cycle is predicted in accordance with the difference. Then, making use of a time within which the computer does not access, data are read out looking-ahead from the image memory based on the predicted read address and are stored into a register, and then, if an actual read address coincides with the predicted address, then the data of the register are transferred, but if they do not coincide with each other, reading of the image memory is performed again but based on the actual read address.
FIG. 10 illustrates the data processing condition of the system described above. In FIG. 10, the waveform (a) schematically illustrates access of the computer, and the waveform (b) schematically illustrates access of a memory controller. In the waveforms (a) and (b) of FIG. 10, reading of data from the image memory by the computer is indicated at T0, T2, T4 and T6, and look-ahead reading processing timings are indicated at T1, T3, T5 and T7. Thus, it can be seen from FIG. 10 that data read in looking-ahead making use of free times which do not interfere with the read timings T0, T2, T4 and T6 of the computer are stored into the data register.
With the system described above, however, no effect of high speed operation can be achieved with irregular image data which are stored at random in the image memory and do not allow prediction of the read address, and since reading processing of the computer and memory access of the memory access controller cannot be performed simultaneously as seen from FIG. 10, the computer has a waiting time. Further, in the system, while comparatively efficient read access can be performed where the processing speed of the CPU of the computer is low, the processing speed of the CPU in recent computers is improved, and in the case of a computer whose CPU has a high processing speed, wasteful waiting time is produced with the CPU.